the technology
A design loop that verifies its own work.
Every revision is measured against real simulation and formal proofs, not a model's guess, so it converges on a design that holds up.
assign s_axi_wready = 1'b1; assign s_axi_wready = ~fifo_full;A stylised illustration.
What we do
From intent to silicon, in one flow.
intent
Design intent
Text, voice, diagrams, schematics or existing RTL: whatever you have, we process it and carry it toward a coherent design.
generate
RTL generation
RTL, testbenches and checks that draw on whatever inputs the design needs, specs, diagrams, existing code and more.
simulate
Design simulation
Behavioural and post-synthesis runs in one workflow, so you and our agents both identify bugs early and know the design still holds after synthesis.
visualise
Schematic studio
See your RTL as interactive schematics, module by module, so you can trace any signal and understand your whole design at a glance.
synthesis
Output analysis
Timing, area and power read back from synthesis, so you see how the design really performs and where to tune it.
program
Program to silicon
The verified bitstream loaded onto real hardware, live on silicon.
How we generate RTL
SMELTR: any input, synthesisable RTL out.
Language, voice, specs, diagrams and schematics go in, whether from you, an agent or the project itself. SMELTR generates synthesisable Verilog and SystemVerilog.
- Language
- Voice
- Specs
- Diagrams
- Schematics
Synthesisable Verilog / SystemVerilog
No manually-written RTL.
the design intent graph
A brain that gets better.
Drag a node to move it
A live model of your whole design: intent, the RTL, the checks and constraints around it, and how every piece connects. Every event, whether from you, an agent or the project, writes straight back to it, so agents always work from the latest context.
How we improve
The design fixes itself before a human ever has to.
Reflexion is a closed-loop verification engine. Every pass is evaluated based on real evidence, simulation waveforms and formal proofs, not the model's own confidence.
Each iteration reads what actually happened, traces the failure back through the graph to the exact block that caused it, patches that block and runs again. The loop closes only when every check passes, converging on RTL that is working and correct rather than merely plausible.
The Reflexion loop
Generate
Agents write the RTL, testbenches and checks straight from the graph.
Run
Agents dispatch simulation and synthesis to the tools on your machine.
Analyse
Agents read the waveforms, timing, area, power and every failing check.
Regenerate
Agents patch the exact block the graph points to, then run it again.
integrations
Runs on your existing tools.
Generated RTL feeds straight into the synthesis and simulation tools you already run, producing real waveforms and proofs. Chipforge drives the loop; the heavy work runs on your own machine.
Chipforgethe loopyour machine
Want to see it on your design?
Get in touch. Tell us what you build. We will route the conversation.